This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2002-122154, filed on Apr. 24, 2002, the entire contents of which are incorporated herein by reference.
The present invention relates to an operational amplifier that uses a bipolar transistor in an output circuit.
Nowadays, semiconductor devices used in various types of electronic equipment are required to have a lower power supply voltage and lower power consumption. Thus, the output voltage of an operational amplifier mounted on a semiconductor device tends to decrease. Accordingly, an operational amplifier that functions under a lower power supply voltage without decreasing its output voltage is required.
FIG. 1 is a schematic circuit diagram of an operational amplifier (hereafter, referred to as op amp) 50 in the prior art. The op amp 50 has a pure complementary output circuit, which includes an NPN source output transistor Tr9 and a PNP sink output transistor Tr7. The op amp 50 uses a bipolar transistor to achieve the required temperature characteristics and large output current and to guarantee reliability in the manufacturing process.
The base of a PNP transistor Tr1 receives an input voltage IN1, and the collector of the PNP transistor Tr1 is connected to the collector of an NPN transistor Tr3. The base of a PNP transistor Tr2 receives an input voltage IN2, and the collector of the PNP transistor Tr2 is connected to the collector of an NPN transistor Tr4. The NPN transistors Tr3 and Tr4 configure a current mirror circuit. The emitters of the transistors Tr1 and Tr2 are connected to a common power supply 1.
The power supply 1 supplies the transistors Tr1 and Tr2 with a constant current in accordance with a power supply Vcc. The bases of the transistors Tr3 and TR4 are connected to the collector of the transistor Tr4. The emitters of the transistors Tr3 and tr4 are connected to the ground GND.
The collectors of the transistors Tr1 and Tr3 are connected to the base of an NPN transistor Tr5. The emitter of the transistor Tr5 is connected to the ground GND. The collector of the transistor Tr5 is connected to the bases of PNP transistors Tr6 and Tr7 and to the collector of the transistor Tr6. The transistors Tr6 and Tr7 configure a current mirror circuit.
The emitter of the transistor Tr6 is connected to the emitter of an NPN transistor Tr8. The emitter of the NPN transistor Tr7 is connected to the emitter of an NPN transistor Tr9. The bases of the transistors Tr8 and Tr9 and the collector of the transistor Tr8 are connected to a current source 2. The current source 2 generates constant current in accordance with the power supply Vcc. The collector of the transistor Tr9 is connected to the power supply Vcc. An output signal Vout is generated at the emitters of the transistors Tr9 and Tr7.
In the op amp 50, when the input voltage IN2 is greater than the input voltage IN1, the collector current of the transistor Tr2 decreases, and the base current of the transistors Tr3 and Tr4 decreases. This decreases the collector current of the transistors Tr3 and Tr4.
Since the collector current of the transistor Tr1 does not change, the base current of the transistor Tr5 increases. As a result, the collector current of the transistors Tr6 and Tr7 increases. The base current of the transistors Tr8 and Tr9 are constant in accordance with the current source 2. Thus, the collector current of the transistors Tr8 and Tr9 is constant. Accordingly, the output voltage Vout decreases.
When the input voltage IN2 is less than the input voltage IN1, the collector current of the transistor Tr2 increases, and the base current of the transistors Tr3 and Tr4 increases. This increases the collector current of the transistors Tr3 and Tr4.
Since the collector current of the transistor Tr1 does not change, the base current of the transistor Tr5 decreases. As a result, the collector current of the transistors Tr6 and Tr7 decreases. The base current of the transistors Tr8 and Tr9 is constant in accordance with the current source 2. Thus, the collector current of the transistors Tr8 and Tr9 is constant. Accordingly, the output voltage Vout increases.
In the op amp 50, the idling current of the transistors Tr9 and Tr7 may be set at a small value with the current source 2. However, in the op amp 50, the maximum output voltage VoutH is less than the power supply Vcc by at least an amount corresponding to the base-emitter voltage drop VBE. The minimum output voltage VoutL is greater than the power supply Vcc by at least an amount corresponding to the base-emitter voltage drop VBE. Accordingly, when decreasing the amplitude of the output voltage Vout to decrease the power supply voltage, the amplitude of the output voltage is insufficient.
The transistor Tr5 is arranged between the transistors Tr1, Tr2 and the transistors Tr9, Tr7. This decreases the response speed of the output voltage Vout relative to the input voltages IN1 and IN2.
FIG. 2 illustrates another op amp 50A in the prior art. Output transistors Tr16 and Tr18 are both NPN transistors. The op amp 50A includes a sub-complementary output circuit.
The base of a PNP transistor Tr11 receives an input voltage IN3, and the collector of the PNP transistor Tr11 is connected to the collector of an NPN transistor Tr13. The base of a PNP transistor Tr12 receives an input voltage IN4, and the collector of the PNP transistor Tr12 is connected to the collector of an NPN transistor Tr14. The NPN transistors Tr13 and Tr14 configure a current mirror circuit. The emitters of the transistors Tr11 and Tr12 are connected to a common power supply 3.
When the input voltage IN4 is greater than the input voltage IN3, the collector current of the transistor Tr12 decreases. Thus, the base current of an NPN transistor Tr15 decreases, and the collector current of the transistor Tr15 decreases. When the collector current of the transistor Tr15 decreases, the base current of the NPN source output transistor Tr16 increases, and the collector current of the output transistor Tr16 increases.
Further, when the collector current of the transistor Tr15 decreases, the base current of a PNP transistor Tr17 decreases, and the collector current of the transistor Tr17 decreases. When the collector current of the transistor Tr17 decreases, the base current of an output transistor Tr18 decreases, and the collector current of the output transistor Tr18 decreases.
When the input voltage IN4 is less than the input voltage IN3, the collector current of the transistor Tr12 increases. Thus, the base current of the transistor Tr15 increases, and the collector current of the transistor Tr15 increases. When the collector current of the transistors Tr15 increases, the base current of the output transistor Tr16 decreases, and the collector current of the output transistor Tr16 decreases.
Further, when the collector current of the transistor Tr15 increases, the base current of a PNP transistor Tr17 increases, and the collector current of the transistor Tr17 increases. When the collector current of the transistor Tr17 increases, the base current of the NPN sink output transistor Tr18 increases, and the collector current of the output transistor Tr18 increases.
The collector current of the transistor Tr17 is supplied as the collector current of the NPN transistor Tr19. An idling current setting circuit, which includes transistors Tr20 to Tr22 and a resistor R, control the base current of the transistor Tr19.
The idling current setting circuit detects the output voltage Vout and increases the base current of the transistor Tr19 when the output voltage Vout increases to increase the collector current of the transistor Tr19. When the output voltage Vout decreases, the idling current setting circuit decreases the base current of the transistor Tr19 to decrease the collector current of the transistor Tr19.
The base potential VB19 at the transistor Tr19 is greater than the output voltage Vout by an amount corresponding to the base-emitter voltage drops VBE16, VBE17, and VBE19 at the corresponding transistors Tr16, Tr17, and Tr19. Further, the base potential VB19 is greater than the output voltage Vout by an amount corresponding to the base-emitter voltage drops VBE20, VBE21, and VBE22 at the corresponding transistors Tr20, Tr21, and Tr22. Accordingly, the base-emitter voltage drop VBE20 of the transistor Tr20 is about the same as the base-emitter voltage drop VBE16 of the transistor Tr16.
In the op amp 50A, when the collector current of the transistor Tr15 increases in accordance with the input voltages IN3 and IN4, the collector current of the output transistor Tr16 decreases, the collector current of the output transistor Tr18 increases, and the output voltage Vo decreases. When the collector current of the transistor Tr15 decreases in accordance with the input voltages IN3 and IN4, the collector current of the output transistor Tr16 increases, the collector current of the output transistor Tr18 decreases, and the output voltage Vo increases.
In this state, the idling current that flows through the output transistor Tr16 is set by the base-emitter voltage drop at the transistor Tr20, and the idling current of the transistor Tr18 is set by the collector current of the transistor Tr20. When the tolerable supply current I1 and I2 of the current sources 4 and 5 are the same, the idling current Id that flows to the ground GND from the power source Vcc via the output transistors Tr16 and Tr18 is expressed by the following equation, in which Q16, Q17, Q19, Q20, Q21, and Q22 respectively represent the sizes of the transistors Tr16, Tr17, Tr19, Tr20, Tr21, and Tr22.
Id=I2xc3x97(Q19/Q22)xc3x97(Q17/Q21)xc3x97(Q16/Q20)
In the op amp 50A, the sink output transistor Tr18 of the sub-complementary output circuit is an NPN transistor. Thus, the minimum output voltage VoutL substantially decreases to the ground GND level. However, to have the idling current setting circuit function normally, a potential difference that is greater than at least the sum of the base-emitter voltage drops VBE20 to VBE22 is necessary between the output voltage Vout and the power supply Vcc. Accordingly, the maximum output voltage VoutH cannot be sufficiently increased to the level of the power supply Vcc.
To decrease power consumption, the idling current Id must be reduced. To reduce the idling current Id, the current source 5, the supply current I2 of the current source 5 may be reduced. However, the reduction of the supply current I2 reduces the maximum output current of the output transistor Tr18 and decreases the load drive capacity. Accordingly, the idling current Id cannot be reduced while maintaining the load drive capacity
A Darlington-connected source output transistor Tr16 may be used to increase the output current of the source output transistor Tr16 and improve the load drive capacity. In such a case, to match the base-emitter voltage drops VBE16 and VBE20 of the output transistor Tr16 and the transistor Tr20, a diode-connected transistor may be arranged between the bases of the transistors Tr16 and Tr17. This would cause the supply current I1 of the current source 4 to affect the value of the voltage drop VBE16. As a result, differences between transistors increase the fluctuation of the idling current Id.
In the op amp 50A, the transistors Tr15 and Tr17 are arranged between the input transistors Tr11, Tr12 and the output transistors Tr16, Tr18. This decreases the response speed of the output voltage Vout relative to the input voltages IN3 and IN4.
One aspect of the present invention is an operational amplifier for use with high and low potential power supplies and for receiving an input current. The operational amplifier includes a first output transistor connected to the high potential power supply and having a control terminal. A second output transistor is connected between the first output transistor and the low potential power supply and has a control terminal, with an output voltage being available at an output node between the first output transistor and the second output transistor. A drive unit is connected to the first and second output transistors to drive the first and second output transistors in accordance with the input current. The drive unit includes a current source connected to the high potential power supply. A first current mirror circuit is connected to the current source. A second current mirror circuit is connected between the first current mirror circuit and the low potential power supply. The input current is supplied to a first node between the first and second current mirror circuits. The control terminal of the second output transistor is connected to the first node, and the control terminal of the first output transistor is connected to a second node between the current source and the first current mirror circuit.
A further aspect of the present invention is an operational amplifier for use with high and low potential power supplies and for receiving an input current. The operational amplifier includes a first output transistor connected to the high potential power supply and having a control terminal. A second output transistor is connected between the first output transistor and the low potential power supply and having a control terminal, with an output voltage being available at an output node between the first output transistor and the second output transistor. A drive unit is connected to the first and second output transistors to drive the first and second output transistors in accordance with the input current. The drive unit includes a current source connected to the high potential power supply. A first current mirror circuit is connected to the current source. A second current mirror circuit is connected between the first current mirror circuit and the low potential power supply. A first resistor is connected between the second current mirror circuit and the low potential power supply. The control terminal of the second output transistor is connected to a first node between the first and second current mirror circuits. The control terminal of the first output transistor is connected to a second node between the current source and the first current mirror circuit. The input current is supplied to a third node between the second current mirror circuit and the first resistor.
A further aspect of the present invention is an operational amplifier for use with high and low potential power supplies and a current source. The operational amplifier includes a first PNP transistor having a collector connected to the current source, a base connected to the collector, and an emitter connected to a high potential power supply. A second PNP transistor has a base connected to the base of the first PNP transistor and an emitter connected to the high potential power supply. A third PNP transistor has an emitter connected to a collector of the second PNP transistor. A fourth PNP transistor has an emitter connected to the collector of the second PNP transistor and to the emitter of the third PNP transistor. A fifth PNP transistor has a base connected to the bases of the first and second PNP transistors and an emitter connected to the high potential power supply. A sixth PNP transistor has a base connected to the base of the fifth PNP transistor and an emitter connected to the high potential power supply. A first NPN transistor has a collector and a base connected to a collector of the fifth PNP transistor and an emitter connected to a collector of the fourth PNP transistor. A second NPN transistor has a base connected to the base of the fifth PNP transistor, a collector connected to the collector of the sixth PNP transistor, and an emitter connected to a collector of the third PNP transistor. A third NPN transistor has a collector and a base connected to the emitter of the first NPN transistor and an emitter connected to the low potential power supply. A fourth NPN transistor has a collector connected to the emitter of the second NPN transistor, a base connected to the base of the third NPN transistor, and an emitter connected to the low potential power supply. A seventh PNP transistor has an emitter connected to the high potential power supply and a base connected to the collectors of the sixth PNP transistor and the second NPN transistor. A fifth NPN transistor has a collector connected to a collector of the seventh PNP transistor, a base connected to the emitter of the second NPN transistor and to the collector of the fourth NPN transistor, and an emitter connected to the low potential power supply.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.